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M5Unit-IMU 0.0.2 git rev:e5b00aa
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Framework-agnostic detection of a classic/host built-in accel+gyro IMU. More...
#include <cstdint>#include <initializer_list>Go to the source code of this file.
Namespaces | |
| namespace | m5 |
| Top level namespace of M5Stack. | |
Enumerations | |
| enum class | m5::unit::imu::ImuKind : uint8_t { None , MPU6050 , MPU6886 , MPU9250 , BMI270 , SH200Q } |
| Which built-in accel/gyro chip a host carries. More... | |
Functions | |
| template<class ReadReg > | |
| ImuKind | m5::unit::imu::detectBuiltinImu (ReadReg read) |
| Probe the internal bus for a built-in accel/gyro chip. | |
Framework-agnostic detection of a classic/host built-in accel+gyro IMU.
Several M5Stack hosts carry a version-dependent accel/gyro chip that M5.getBoard() cannot distinguish: e.g. Core2 v1.1 has an MPU6886 while Core2 v1.3 has a BMI270, and ATOM Matrix switched from MPU6886 to BMI270 at v1.1 – both report the same board id. detectBuiltinImu() probes the internal bus (via an injected read callback, so src/ stays free of M5Unified / Arduino Wire – same pattern as m5::unit::bmi270::detectAddress and m5::unit::imu::detectBuiltinMag) and reports which accel/gyro chip is actually present, so the caller can construct the matching driver. The probe order mirrors M5Unified's IMU_Class::begin(): MPU family first (WHO_AM_I), then BMI270 (CHIP_ID at 0x68/0x69), then SH200Q. Note: m5::unit::imu here is distinct from the m5::imu namespace that holds the AHRS types.
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Which built-in accel/gyro chip a host carries.
| ImuKind m5::unit::imu::detectBuiltinImu | ( | ReadReg | read | ) |
Probe the internal bus for a built-in accel/gyro chip.
| ReadReg | Callable bool(uint8_t addr, uint8_t reg, uint8_t& out) returning true on ACK |
| read | The bus read callable |
The MPU family shares WHO_AM_I register 0x75 at 0x68 (MPU6886=0x19, MPU6050=0x68, MPU9250=0x71) and is resolved first, so a BMI270 (whose 0x75 is undefined) is never mistaken for an MPU. Then the BMI270 CHIP_ID (0x24 at register 0x00) is checked at both candidate addresses 0x68 and 0x69. Finally SH200Q is checked by its WHO_AM_I (0x18 at register 0x30, address 0x6C). This is detection only: it does not initialise or reset any chip.